1. Field of the Invention
This invention relates to a sample-and-hold circuit.
2. Description of the Related Art
Sample-and-hold circuits are widely used to store an analog voltage accurately over a time ranging from nanoseconds to minutes.
Sample-and-hold circuits are also used in liquid-crystal display (LCDs). In a LCD television picture display, a given line of video information is broken into the same number of pieces as there are pixels in the horizontal row, and stored in the sample-and-hold stages which all drive their respective drain bus of switching matrix simultaneously, thus creating a line sequential display (vide, for example, D. G. Fink and D. Christiansen, Electronics Engineers' Handbook, Third Edition, McGraw-Hill, New York, 1989, pages 20-102, 20-103).
U.S. patent application Ser. No. 07/868,213, filed on Apr. 14, 1992 of Shinichi URANAKA for Sample-and-hold circuit, claiming the benefit of Japanese Patent Application 082396/91 filed on Apr. 15, 1991, describes a improved sample-and-hold circuit with only one operational amplifier for use in driver of an active matrix addressed LCD.
Referring now to FIG. 3, there is shown in detail a MOS transistor circuit version of the sample-and-hold circuit described in the above mentioned U.S. Patent Application. An input voltage signal VI1 is applied to a capacitor C1 through an analog switch or MOS transistor switch G1, and an input voltage signal VI2 is applied to a capacitor C2 through an analog switch or MOS transistor switch G2. The capacitors C1 and C2 are quickly charged when the switches G1 and G2 are turned on in the sampling mode. The switches G1 and G2 are turned off in the hold mode.
Either one of the capacitors C1 and C2 is selected by input switching signals CNT and CNT', the signal CNT' being the complement of the signal CNT. The value of the voltage across the selected charged capacitor is presented to the output through an output circuit that produces unity voltage gain as an output voltage signal Vout. The output circuit comprises cascaded differential and buffer amplifiers having a feedback connection between them. The differential amplifier, which has two non-inverting and one inverting inputs, comprises n-channel MOS transistors N3, N10, N11, N12, N20, N21 and N22, and p-channel MOS transistors P0 and P1. The buffer amplifier comprises n-channel MOS transistors N4 and N5.
An output circuit comprising cascaded differential and buffer amplifiers having a feedback connection between them is disclosed in U.S. patent application Ser. No. 07/774,830, filed on Oct. 11, 1991 of Junji TANAKA for Analog Signal Extracting Circuit, claiming the benefit of Japanese Patent application 282872/90 filed on Oct. 19, 1990. But the differential amplifier included in it has only one non-inverting input and no switching transistor connected in series with the input transistor in the non-inverting input leg.
Referring now more particularly to FIG. 3, the gates of input transistors N11 and N12, which constitute the non-inverting inputs of the differential amplifier, are respectively connected to the capacitors C1 and C2. The switching transistors N21 and N22 are respectively connected in series with the input transistors N11 and N12 in non-inverting input legs connected in parallel in the differential amplifier. The input switching signals CNT and CNT' are respectively applied to the gates of switching transistors N21 and N22.
The transistors N10 and N20 are connected in series in the inverting input leg of the differential amplifier. Voltage Vdd is supplied to the gate of the transistor N20 as a bias voltage.
The drain of the transistor N3, which acts as a constant-current source, is connected to the sources of the transistors N20, N21 and N22. The source of the transistor N3 is connected to ground. A bias voltage Vb1 is supplied to the gate of the transistor N3.
The drain of transistor P0 is connected to the drain of transistor N10, and the drain of transistor P1 is connected to the drains of transistor N11 and N12. The sources of the transistors P0 and P1 are connected to supply voltage Vdd. The gates of the transistors P0 and P1 are connected together. The gate and the drain of transistor P1 are connected together. The transistors P0 and P1 mutually connected as explained above constitute a well-known current mirror, which acts as a high active drain resistor of the transistor N11 or N12.
The drain of transistor N10, which constitutes the output of the differential amplifier, is connected to the gate of the transistor N4, which constitutes an input of the buffer amplifier. The gate of the transistor N10, which constitutes the inverting input of the differential amplifier, is connected to the source of the transistore N4 which constitutes the output of the buffer amplifier. The direct connection between the gate of the transistor N10 and the source of the transistor N4 provides operational feedback. The source of the transistor N4 in turn is connected to the output terminal of the output circuit where the output voltage signal Vout is taken. The drain of the transistor N4 is connected to supply voltage Vdd.
The drain of the transistor N5, which acts as a constant-current source, is connected to the source of the transistors N4. The source of the transistor N5 is connected to ground. A bias voltage Vb2 is supplied to the gate of the transistor N5.
The operation of the sample-and-hold circuit mentioned above will be explained with reference to FIG. 4 which shows a timing chart.
When the sampling signal TRF applied to the analog switches G1 and G2 is at a high level (Vdd), both of analog switches G1 and G2 are turned on (conducting), which allow the capacitors C1 and C2 to be respectively charged to the instantaneous voltages of the input signals VI1 and VI2. The period of the sampling signal TRF is for example 63.5 microseconds, that is, the line period of the television system. Now for the sake of explanation, input signals VI1 and VI2 are assumed to be the same. However, it should be remarked that both signals are generally different. The transistors N21 and N22 are alternately turned on, because the gates are fed with the input switching signals CNT and CNT', the voltage levels of which are inverted in synchronism with the sampling signal TRF. More specifically, when the input switching signal CNT is at high level (Vdd), transistor N21 is turned on, and the value of the voltage across the charged capacitor C1 is presented to the output of the output circuit comprising differential and buffer amplifiers as the output voltage signal Vout. At this time, transistor N22 remains off, because the input switching signal CNT', which is at low level (ground), is applied to its gate. When the input switching signal CNT' is raised to high level (Vdd) at the instant t1, transistor N22 is turned on, and the value of the voltage on the charged capacitor C2 is presented to the output through the output circuit comprising differential and buffer amplifiers.
The sample-and-hold circuit explained above has the following deficiencies. When the sampling signal TRF is at high level, causing the capacitors C1 and C2 to charge, the voltage at high level is applied to the gate of transistor N21, whereas the voltage at low level (ground) is applied to the gate of transistor N22. However, for the purpose of causing the voltage across the capacitor C2 to be available at the output of the output circuit, the gate voltage of switching transistor N22 makes transition from low level to high level at the instant t1, when the sampling signal TRF is at low level and the switch G2 remains off. The transistor N22 is turned on, and a change in the source voltage of the transistor N12 occurs. This change affects the capacitor C2 through the gate-to-source capacitance of the transistor N12, causing the voltage across the charged capacitor C2 to vary or shift by a small voltage. On the contrary to that, for the purpose of causing the voltage across the capacitor C1 to be available at the output of the output circuit, the gate voltage of switching transistor N21 makes transition from low level to high level at the instant when the sampling signal TRF goes toward high level and the capacitor C1 becomes charged through the switch G1. There is no such variation or shift of the voltage across the capacitor C1 as explained above. Therefore, the output voltage Vout shows a variation .delta. as illustrated in FIG. 4, even though the same input signals are sampled.